PD17012_15 Datasheet, PDF (69/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
Table 8-1. Peripheral Hardware Control Functions of Control Registers (3/4)
Control Register
Peripheral Hardware Control Function
After Reset
Name
b3
Read/ b2
Address
Write b1
b0
Functional Outline
Set Value
0
1
SC
TE
O
P
Serial I/O
mode select
register
PLL unlock
FF judge
register
02H
SIO1TS Starts/stops operation
Stops operation Starts operation
––––––––––––––––––––– ––––––––––––––––––––– ––––––––––––––––––
SIO1HIZ Sets SO1 pin as serial output pin
General-purpose
I/O port
Serial output
R/W ^{– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –} 0 0 0
SIO1CK1
0
0
1
1
– – – – – – – – – _{Sets clock of serial interface}
External 37.5 kHz 75 kHz 450 kHz
clock
SIO1CK0
0
1
0
1
05H
0
–––––––––
0
Fixed to 0
R&Reset ^{– – – – – – – – –}
0
––––––––––––––––––––– ––––––––––––––––––––– ––––––––––––––––––
PLLUL
Detects status of unlock FF
Lock status Unlock status
PLL mode
select
21H
register
PLL
reference
31H
clock select
register
0
– – – – – – – – – _{Fixed to 0}
0
R/W – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 0 0
PLLMD1
0
0
1
1
– – – – – – – – – _{Sets division method of PLL}
PLLMD0
Disable MF
0
1
VHF HF
0
1
R/W
PLLRFCK3
–––––––––
PLLRFCK2
–––––––––
PLLRFCK1
–––––––––
PLLRFCK0
Sets reference frequency of PLL
0: 1.25 kHz, 1: 2.5 kHz, 2: 5 kHz,
3: 10 kHz, 4: 6.25 kHz,
5: 12.5 kHz, 6: 25 kHz, 7: 50
kHz, 8: 3 kHz, 9, A, B: Setting
F
F
prohibited, C: 1 kHz, D: 9 kHz, E:
100 kHz, F: Off
IF counter
gate judge 04H
register
IF counter
mode select ^12H
register
IF counter
control
23H
register
0
–––––––––
0
Fixed to 0
R ^{–––––––––}
00
0
––––––––––––––––––––– ––––––––––––––––––––– ––––––––––––––––––
IFCG
Detects opening/closing of gate of frequency counter
Close
Open
IFCMD1
0
0
1
1
– – – – – – – – – Sets mode of frequency counter
FCG
AMIFC pin
FMIFC pin FMIFC pin
R/W
–
IFCMD0
––––––
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–⁰–
–
–
–
AMIF mode
–¹ – – – –
–
FMIF mode AMIF mode
0_{– – – – –}1_{– – – – –}
0
0
IFCCK1
0
0
1
1
– – – – – – – – – Sets gate time of frequency counter
IFCCK0
1 ms 4 ms
8 ms Open
1 kHz 100 kHz 900 kHz
0
1
0
1
0
– – – – – – – – – Fixed to 0
0
W ^{––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––} 0 0
IFCSTRT Starts counting of IF counter
Does not start
Starts
––––––––––––––––––––– ––––––––––––––––––––– ––––––––––––––––––
IFCRES Resets IF counter
Does not reset
Resets
FCG
channel
24H
select
register
BEEP select
register
15H
0
– – – – – – – – – Fixed to 0
0
R/W – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 3 3
FCGCH1
0
0
1
1
– – – – – – – – – _{Sets pin to be used as FCG}
FCGCH0
FCG0 FCG1 Not Not
used used
0
1
0
1
0
– – – – – – – – – _{Fixed to 0}
0
R/W ^{– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –} 0 0 0
BEEP1SEL BEEP1 pin
General-
–––––––––
Set as BEEP
purpose
BEEP
BEEP0SEL BEEP0 pin
I/O port
Data Sheet U10101EJ4V0DS
67