PD17012_15 Datasheet, PDF (107/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
11.6 Acknowledging Interrupts
11.6.1 Acknowledging interrupts and priority
An interrupt is acknowledged in the following procedure:
(1) Each peripheral hardware unit outputs an interrupt request signal to the corresponding interrupt control block
if a given interrupt condition is satisfied (e.g., if a rising signal is input to the INT pin).
(2) When the interrupt control block has received the interrupt request signal from the peripheral hardware unit,
it sets the corresponding interrupt request flag (e.g., IRQ flag if the peripheral unit is the INT pin) to 1.
(3) If the interrupt enable flag corresponding to the interrupt request flag (e.g., IP flag for IRQ flag) is set to 1 when
the interrupt request flag is set to 1, the interrupt control block outputs 1.
(4) The signal output by the interrupt control block is ORed with the output of the interrupt enable flip-flop, and
an interrupt acknowledge signal is output.
This interrupt enable flip-flop is set to 1 by the EI instruction and reset to 0 by the DI instruction.
If the interrupt control block outputs 1 while the interrupt enable flip-flop is 1, the interrupt is acknowledged.
As shown in Figure 11-1, the interrupt acknowledge signal is input to each interrupt control block when the
interrupt has been acknowledged.
The interrupt request flag is reset to 0 by the signal input to the interrupt control block, and a vector address
corresponding to the interrupt is output.
If more than one interrupt block outputs 1 at this time, the interrupt acknowledge signal is not transferred to
the next stage. If more than one interrupt request is issued at the same time, therefore, the interrupts are
acknowledged in the following priority order.
INT pin > 12-bit timer > basic timer 1 > serial interface
The interrupt of an interrupt source is not acknowledged unless the corresponding interrupt enable flag is
set to 1.
If the interrupt enable flag is reset to 0, therefore, an interrupt with a high hardware priority can be disabled.
Data Sheet U10101EJ4V0DS
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