PD17012_15 Datasheet, PDF (256/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
21.4 Halt Function
The halt function stops the operation clock of the CPU by executing the HALT h instruction.
When the HALT h instruction is executed, the program stops at the HALT h instruction, until the halt status
is released later.
Therefore, the current consumption of the device can be reduced in the halt status by the operating current
of the CPU.
The halt status can be released by key input, timer carry, or interrupt.
The releasing condition of the key input, timer carry, and interrupt is specified by the operand “h” of the HALT
h instruction.
The HALT h instruction is valid regardless of the input level of the CE pin.
The following subsections 21.4.1 through 21.4.6 explain the halt status, halt release condition, and each halt
release condition.
21.4.1 Halt status
All the operations of the CPU are stopped in the halt status.
In other words, program execution is stopped at the HALT h instruction.
However, the peripheral hardware units continue the operations set before the HALT h instruction is executed.
For the operations of the peripheral hardware units, refer to 21.6 Device Operations in Halt and Clock Stop
Status.
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Data Sheet U10101EJ4V0DS