PD17012_15 Datasheet, PDF (283/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
(2) Restoring from clock stop status
To restore the device from the back-up status while supply voltage VDD is backed up at 2.3 V by using
the clock stop instruction, VDD must be raised to 3.5 V or higher within 50 ms after the CE pin has gone
high.
As shown in Figure 22-8, the device is restored from the clock stop status by means of CE reset. Because
the power-on clear voltage is changed to 3.5 V 50 ms after the CE pin has gone high, power-on reset
is effected unless VDD is 3.5 V or higher at this point.
The same applies when VDD is lowered.
Figure 22-8. Restoring from Clock Stop Status
5V
3.5 V
VDD _{2.3 V}
0V
H
CE
L
H
XOUT
L
Basic timer 0 carry ^H
FF setting pulse _L
Power-on- ^H
clear signal _L
Back up by clock
stop instruction
Halt status
50 ms
Normal operation
Processing
where
CE = low
Back up
CE reset
Program starts
STOP s
instruction
Power-on clear voltage is
changed to 3.5 V at this point.
Therefore, VDD must rise to 3.5 V
or higher before this point.
Power-on clear voltage is
changed to 2.3 V at this point.
Therefore, VDD must not fall
below 3.5 V before this point.
Power-on-
clear voltage
Data Sheet U10101EJ4V0DS
281