PD17012_15 Datasheet, PDF (206/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
(a) Resetting the gate to other than open by using IFCCK1 and IFCCK0 flags
Gate
OPEN
CLOSE
Count period
IFCCK1 = IFCCK0 = 1
Resetting the gate to other than open
by IFCCK1 and IFCCK0 flags
(b) Unselect pin used by using IFCMD1 and IFCMD0 flags
In this way, the gate remains open, and counting is stopped by disabling input from the pin.
Gate ^OPEN
CLOSE
Count period
Sets IFCCK1 = IFCCK0 = 1
Sets IFCMD1 = IFCMD0 = 0 (FCG)
FMIFC and AMIFC pins are unselected and
count signal cannot be input
17.3.3 Gate operation when external gate counter function is selected
The gate is opened from the rising to the next rising of the signal input to a selected pin after the IFCSTRT flag
has been set to 1, as illustrated below.
While the gate is open, the internal frequency (1 kHz, 100 kHz, 900 kHz) is counted by a 16-bit counter.
The IFCG flag is set to 1 from the rising to the next rising of the external signal after the IFCSTRT flag has been
set.
In other words, the opening or closing of the gate cannot be detected by the IFCG flag when the external gate
counter function is selected.
H
External signal
L
Gate ^OPEN
CLOSE
Count period
Gate is opened at
this point
IFCSTRT flag ← 1
End of counting
IFCG flag is “0”
If reset and started while gate is open
H
External signal
L
Gate ^OPEN
CLOSE
Count period
Count period
IFCSTRT flag ← 1
Gate is opened at
this point
IFCSTRT flag ← 1
End of counting
IFCG flag is “0”
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Data Sheet U10101EJ4V0DS