PD17012_15 Datasheet, PDF (101/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
11.2 Interrupt Control Block
The interrupt control block is provided for each peripheral hardware unit and detects an interrupt request,
enables the interrupt, and generates a vector address when the interrupt is acknowledged.
11.2.1 Configuration and function of interrupt request flag (IRQ×××)
Each interrupt request flag (IRQ×××) is set to 1 when an interrupt request is issued from the corresponding
peripheral hardware unit, and is reset to 0 when the interrupt is acknowledged. It cannot be set by software.
The issued state of each interrupt request can be detected by the detection of these interrupt request flags
when interrupts are not enabled.
Also, when 1 is directly written to the interrupt request flag via a window register, it means that the interrupt
request has been issued.
Once this flag has been set to 1, it is not reset until the corresponding interrupt is acknowledged or 0 is written
via a window register.
If more than one interrupt request is issued at the same time, the interrupt request flag corresponding to the
interrupt that has not been acknowledged is not reset.
The interrupt request flag is assigned to the register file’s interrupt request register.
The configuration and function of the interrupt request register are shown in Figures 11-2 to 11-5.
Figure 11-2. Configuration of Interrupt Request Register 1
Name
Flag symbol
b3 b2 b1 b0
Interrupt request register 1 I 0 0 I
N
R
T
Q
Address
3FH
Read/
write
Bit 3: R
Bit 0: R/W
Power-on
Clock stop
CE
Sets interrupt request issuing status of INT pin
0 Interrupt request not issued
1 Interrupt request issued
Fixed to 0
Detects status of INT pin
0
Low level is input
1
High level is input
0000
0
0
0
0
Data Sheet U10101EJ4V0DS
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