PD17012_15 Datasheet, PDF (128/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
(4) If BTM0CY flag is detected at the same time as CE reset
As described in (3) above, CE reset is effected as soon as the BTM0CY flag is set to 1.
If the instruction that reads the BTM0CY flag happens to be executed at the same time as CE reset at
this time, the BTM0CY flag reading instruction takes precedence.
Therefore, if the next setting the BTM0CY flag (rising of BTM0CY flag setting pulse) after the CE pin has
gone high coincides with execution of the BTM0CY flag reading instruction, CE reset is effected at the
next timing at which the BTM0CY flag is set.
This operation is illustrated in Figure 12-10.
Figure 12-10. Operation When CE Reset Coincides with BTM0CY Flag Reading Instruction
H
CE pin
L
H
BTM0CY flag
setting pulse _L
1
BTM0CY flag
0
SKT1
BTM0CY
SKT1
BTM0CY
CE reset
H
BTM0CY flag
setting pulse _L
1
BTM0CY flag
0
Instruction
SKT1 BTM0CY
(PEEK ···)
4.44 µs
(SKT ···)
Embedded macro
PEEK WR, . MF. BTM0CY SHR 4
SKT WR, #. DF. BTM0CY AND 000FH
If BTM0CY flag is read at this time, CE reset is
effected delayed once.
Originally, program is started from address 0000H here.
However, CE reset is not effected because it happens to
coincide with program that reads BTM0CY flag.
Consequently, if the BTM0CY flag detection time interval coincides with the BTM0CY flag setting time
in a program that cyclically detects the BTM0CY flag, CE reset is never effected.
Therefore, the following point must be noted.
Because one instruction cycle is 4.44 µs (1/225 kHz), a program that detects the BTM0CY flag once, for
example, every 225 instructions, reads the BTM0CY flag every 4.44 µs × 225 = 1 ms.
Even if any of 1 ms, 5 ms, 100ms, or 250 ms is selected as the timer time setting pulse, if setting and
detection of the BTM0CY flag coincide once, CE reset is never effected.
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Data Sheet U10101EJ4V0DS