PD17012_15 Datasheet, PDF (118/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
12.2.2 Clock select block
The clock select block divides the system clock (4.5 MHz) and sets the time interval at which the BTM0CY
flag is to be set, by using the basic timer clock select register.
Figure 12-3 shows the configuration of the basic timer clock select register.
Figure 12-3. Configuration of Basic Timer Clock Select Register
Name
Basic timer clock select
register
Flag symbol
b3 b2 b1 b0
BB BB
TT TT
MM MM
11 00
CC CC
KK KK
10 10
Address
09H
Read/
write
R/W
Sets time interval at which BTM0CY flag is set
0 0 100 ms (10 Hz)
0 1 250 ms (4 Hz)
1 0 5 ms (200 Hz)
1 1 1 ms (1 kHz)
00
01
10
11
Sets time interval at which IRQBTM1 flag is set^Note
100 ms (10 Hz)
250 ms (4 Hz)
5 ms (200 Hz)
1 ms (1 kHz)
Power-on
Clock stop
CE
0000
0000
Retained
Note For Basic timer 1, refer to 12.3.
116
Data Sheet U10101EJ4V0DS