PD17012_15 Datasheet, PDF (184/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.3.2 Functions of input select block and programmable divider
The input select block and programmable divider select the input pin and division mode of the PLL frequency
synthesizer.
As the input pin, the VCOH or VCOL pin can be selected.
The selected pin goes into an intermediate-potential state (approx. 1/2 VDD). The pin not selected is internally
pulled down.
These pins input signals via an AC amplifier, and the DC component of the input signal must be cut off by
connecting a capacitor to the pin in series.
Either the direct division mode or pulse swallow mode can be selected as the division mode.
The programmable counter divides the signal input from the VCOH or VCOL pin in a specified division mode
according to the values set to the swallow counter and programmable counter.
Table 16-1 show the input pins (VCOH and VCOL) and division modes.
The input pin and division mode to be used are selected by the PLL mode select register.
16.3.3 explains the configuration and function of the PLL mode select register.
The division ratio is set to the programmable divider by the PLL data register via the data buffer.
16.3.4 explains the programmable divider and PLL data register.
Table 16-1. Input Pins and Division Modes
Division Mode
Pin
Direct division
(MF)
Pulse swallow
(HF)
Pulse swallow
(VHF)
VCOL
VCOL
VCOH
Input Frequency
(MHz)
0.5 to 20
Input Amplitude
(Vp-p)
0.3
Settable Division
Ratio
16 to 2¹² – 1
5 to 30
0.3
256 to 2¹⁶ – 1
Division Ratio Settable in
Data Buffer
010×H to FFF×H
(×: lower 4 bits are arbitrary)
0100H to FFFFH
50 to 150
30 to 250
0.3
256 to 2¹⁶ – 1
0100H to FFFFH
182
Data Sheet U10101EJ4V0DS