PD17012_15 Datasheet, PDF (168/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
15.1 Configuration of Serial Interface
Figure 15-2 shows the configuration of the serial interface.
As shown in the figure, the shift clock control block of the serial interface consists of a clock I/O pin control
block, clock generation block, wait control block, and clock count block.
The serial data control block consists of a serial data I/O pin control block and a presettable shift register.
These blocks are controlled by the corresponding flags of the control registers.
Data is written to or read from the presettable shift register via the data buffer.
The following section 15.2 outlines each block.
Figure 15-2. Configuration of Serial Interface
Control register
Address
02H
Flag
symbol
S S SS
I I II
O O OO
1 1 11
T H CC
S I KK
Z10
Shift clock I/O pin control block
P0A2/SCK1
P0A2/SCK1
output control
Output
latch
WRITE
port
register
READ
P0ABIO2 flag
Serial data I/O pin control block
P0A1/SO1
P0A0/SI1
P0A1/SO1
output control
Output
latch
WRITE
port
register
READ
P0ABIO1 flag
Output
latch
WRITE
port
register
READ
WAIT
Shift clock output
CLKOUT
clock
control
SF8
Wait control
SF8
Clock
counter
Serial clock input
Address
Symbol
Data
Data buffer (DBF)
0CH 0DH 0EH
DBF3 DBF2 DBF1
M
S
B
0FH
DBF0
L
S
B
Serial out data
03H
CLKIN
DATAOUT
DATAIN
Presettable shift register
P0ABIO0 flag
Serial in data
166
Data Sheet U10101EJ4V0DS