PD17012_15 Datasheet, PDF (252/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
20.7 Status on Reset
20.7.1 On power-on reset
The LCD19/P2H0 to LCD0/KS0/PYA0 pins are specified as the LCD segment signal output pins and output a
low level (display off). A low level is output as the key source signal.
20.7.2 On execution of clock stop instruction
The LCD19/P2H0 to LCD0/KS0/PYA0 pins are specified as the LCD segment signal output pins and output a
low level (display off). A low level is output as the key source signal.
20.7.3 On CE reset
The output data is retained as is if the key source signal is being output.
20.7.4 In halt status
The output data is retained as is if the key source signal is being output.
If key input is specified as a halt status releasing condition, the halt status is released when a high level is
input to the P0D3/K3 to P0D0/K0 pins.
If the key source controller is used, however, the halt status is released only by a high level that is input within
220 µs during which the key source data is output.
For an explanation of how to release the halt status by key input, refer to 21.4 Halt Function.
Figure 20-11. KEYJ Flag Status in Halt Status
H
Key input pin
L
1
KEYJ flag
0
Halt status
Halt released status
Halt is released by inputting
INT or TMCY (timer carry)
KEYJ flag is not set in halt status
KEYJ flag is set at this point
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Data Sheet U10101EJ4V0DS