PD17012_15 Datasheet, PDF (54/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
6.3 Address Generation of General Register by Instructions
The following subsections 6.3.1 and 6.3.2 explain how the addresses of the general register are generated
when each instruction is executed.
For details of the operation of each instruction, refer to 7. ALU (Arithmetic Logic Unit) BLOCK.
6.3.1 Addition (“ADD r, m”, “ADDC r, m”),
subtraction (“SUB r, m”, “SUBC r, m”),
logical operation (“AND r, m”, “OR r, m”, “XOR r, m”),
direct transfer (“LD r, m”, “ST m, r”),
and rotation processing (“RORC r”) instructions
Table 6-1 shows the address of general register “R” specified by operand “r” of an instruction. Only the column
address is specified as operand “r”.
Table 6-1. Address Generation of General Register
General register address
Bank
Row Address Column Address
b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0
Contents of general
R
register pointer
r
6.3.2 Indirect transfer (“MOV @r,m”, “MOV m, @r”) instructions
Table 6-2 shows the address of the general register “R” specified by operand “r” of an instruction and an
indirect transfer address specified by “@R”.
Table 6-2. Address Generation of General Register
General register address
Bank
Row Address Column Address
b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0
Contents of general
R
register pointer
r
Indirect transfer address
@R
Same as data memory
Contents of R
52
Data Sheet U10101EJ4V0DS