PD17012_15 Datasheet, PDF (260/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
21.4.4 Releasing halt status by basic timer 0
Releasing the halt status by basic timer 0 is set by the HALT 0010B instruction.
When the release of the halt status is set by basic timer 0, the halt status is released as soon as the basic
timer 0 carry FF has been set to 1.
The basic timer 0 carry FF corresponds to the BTM0CY flag of the basic timer 0 carry FF judge register on
a one-to-one basis, as explained in 12. TIMER, and is set to 1 at fixed time intervals (1 ms, 5 ms, 100 ms, or
250 ms).
Therefore, the halt status can be released at fixed time intervals.
Example
M1
MEM
HLTTMR DAT
0.10H
0010B
; 1-second counter
; Symbol definition
INITFLG
NOT BTM0CK1, BTM0CK0
; Embedded macro
; Sets basic timer 0 carry FF setting time to 250 ms
LOOP:
HALT
SKT1
BR
ADD
SKT1
BR
HLTTMR
; Sets release condition by basic timer 0 carry FF and
halt status
BTM0CY
; Embedded macro
LOOP
; Branches to LOOP if BTM0CY flag is not set
M1, #0100B ; Adds 0100B to contents of M1
CY
; Embedded macro
LOOP
; Executes processing A if carry occurs
Processing A
BR
LOOP
In this example, the halt status is released every 250 ms and processing A is executed every 1 second.
21.4.5 Releasing halt status by interrupt
Releasing the halt status by an interrupt is set by the HALT 1000B instruction.
If releasing the halt status by an interrupt is set, the halt status is released as soon as the interrupt has been
acknowledged.
Four interrupt sources are available as explained in 11. INTERRUPTS.
Therefore, the interrupt source to be used to release the halt status must be specified by program in advance.
So that the interrupt is acknowledged, all the interrupts must be enabled (by the EI instruction), each interrupt
is enabled (by setting the corresponding interrupt enable flag), in addition that the interrupt request must be
issued from each interrupt source.
Even if an interrupt request is issued, if that interrupt is not enabled, the interrupt is not acknowledged and
the halt status is not released.
When the halt status has been released because the interrupt has been acknowledged, the program flow
branches to the vector address of the interrupt.
If the RETI instruction is executed after the interrupt processing, the program flow returns to the instruction
next to the HALT instruction.
Here is an example.
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Data Sheet U10101EJ4V0DS