PD17012_15 Datasheet, PDF (174/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
15.5 Clock Counter
The clock counter is a wrap-around counter that counts the number of the shift clocks output from or input
to the shift clock (P0A2/SCK1) pin.
The clock counter directly reads the status of the shift clock pin. At this time, whether the clock is the internal
clock or an external clock is not identified.
The clock counter does not operate in the wait status of serial communication.
When the value of the clock counter is 8, serial communication is placed in the wait status at the rising edge
of the shift clock.
The contents of the clock counter cannot be directly read by program.
The following subsections 15.5.1 and 15.5.2 explain the operation of the clock counter and the conditions
under which the clock counter is reset.
15.5.1 Operation of clock counter
Figure 15-3 shows the operation of the clock counter.
The initial value of the clock counter is 0. The value of the clock counter is incremented by one each time
the falling of the shift clock pin is detected. When the value of the clock counter has been incremented to 8,
the clock counter is reset to 0 at the next rising edge of the shift clock pin.
Serial communication is placed in the wait status when the clock counter has been reset to 0.
Figure 15-3. Operation of Clock Counter
H
Shift
clock pin
L
H
Serial
data pin
L
1
2
3
D7
D6
D5
7
8
D1
D0
Clock
counter
0
1
2
3
7
80
Resets clock Releases wait
counter
Wait
15.5.2 Clock counter reset condition
The clock counter is reset to 0 when any of the following conditions (1) through (5) is satisfied.
(1) On power-on reset
(2) On execution of the clock stop instruction
(3) When 0 is written to the SIO1TS flag (forced wait)
(4) When the shift clock rises while the value of the clock counter is “8” with the wait status released
(5) On CE reset
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Data Sheet U10101EJ4V0DS