PD17012_15 Datasheet, PDF (176/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
15.6.2 Notes on setting and reading data
Data is written to the presettable shift register by the PUT SIO1SFR, DBF instruction.
Data is read from the register by the GET DBF, SIO1SFR instruction.
Set or read data to or from the register in the wait status. While the wait status is released, the data may
not be correctly set or read depending on the status of the shift clock pin.
Table 15-2 indicates the timing of setting and reading data and points to be noted.
Table 15-2. Reading (GET) and Writing (PUT) Data from/to Presettable Shift Register and Notes
Status on Execution
of PUT/GET
Wait
status
Read (GET)
Write (PUT)
Status of Shift Clock Pin
Operation of Presettable Shift Register (SIO1SFR)
With external clock:
Floated
With internal clock:
Normally the output
latch value is used at
high level.
Normally read.
Normally written.
Content of MSB is output at falling edge of shift clock when wait
status is released next time (during transfer operation).
Clock
Data
MSB
PUT SIO1SFR, DBF Wait released
Wait
released
status
Read (GET)
Write (PUT)
Low level
High level
Low level
Normally read.
Cannot be read normally.
Contents of SIO1SFR are destroyed.
Normally written.
Contents of MSB are output when PUT instruction is executed.
Clock counter is not reset.
Clock
Data
MSB
PUT SIO1SFR, DBF
High level
Cannot be written normally.
Contents of SIO1SFR are destroyed.
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Data Sheet U10101EJ4V0DS