PD17012_15 Datasheet, PDF (63/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
8.2 Configuration and Function of Register File
Figure 8-2 shows the configuration of the register file and its relationship with the data memory.
Addresses are allocated to the register file in 4-bit units, like the data memory, and the register file has a total
of 128 nibbles with row addresses 0H to 7H and column addresses 0H to 0FH.
Control registers that set the conditions of the peripheral hardware units are allocated to addresses 00H to
3FH.
Addresses 40H to 7FH overlap the data memory.
To put it another way, the addresses 40H to 7FH of the register file are the memory addresses of the data
memory bank currently selected.
These addresses, 40H to 7FH, can be treated in the same manner as the normal data memory areas, except
that they can be manipulated by a register file manipulation instruction (“PEEK WR, rf” or “POKE rf, WR”),
because they overlap the data memory.
Figure 8-2. Configuration of Register File and Its Relationship with Data Memory
Column address
0 1 2 3 4 5 6 7 8 9 ABCDEF
0
1
Data memory
2
3
4
5
6
BANK0
7
BANK1
BANK2
System register
0
1
Control register
2
3
Register file
Data Sheet U10101EJ4V0DS
61