PD17012_15 Datasheet, PDF (194/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.7.1 Direct division mode (MF)
(1) Selecting division mode
Select the direct division mode by using the PLL mode select register.
(2) Pin used
When the direct division mode is selected, the VCOL pin is enabled to operate.
(3) Setting reference frequency fr
Set the reference frequency by using the PLL reference clock select register.
(4) Calculating division value N
Calculate as follows:
fVCOL
N=
fr
where,
fVCOL: Input frequency of VCOL pin
fr: Reference frequency
(5) Example of setting PLL data
How to set the data to receive broadcasting in the following MW band is explained below.
Reception frequency: 1,422 kHz (MW band)
Reference frequency: 9 kHz
Intermediate frequency: +450 kHz
Division value N:
fVCOL 1,422 + 450
N=
=
= 208 (decimal)
fr
9
= 0D0H (hexadecimal)
Set data to the PLL data register (PLLR: peripheral address 41H), PLL mode select register (RF address
21H), and PLL reference clock select register (RF address 31H) as follows.
PLL data register (RLLR)
0000
0
11 0 1
D
00 0 0
0
don’t care
PLL mode
PLL reference
select register clock select
register
00 0 1 11 0 1
MF
9 kHz
192
Data Sheet U10101EJ4V0DS