PD17012_15 Datasheet, PDF (234/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
20.2 Functional Outline of Key Source Controller/Decoder
The key source controller/decoder can configure a key matrix of up to 64 keys by using key source signal
output pins (LCD15/KS15/PYA15 to LCD0/KS0/PYA0) and key input pins (P0D3/K3 to P0D0/K0).
Figure 20-2 shows the example of key matrix configuration.
The LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins are multiplexed with LCD segment signal output pins.
Therefore, the key source signals and LCD segment signals are output by means of time-division multiplexing.
The following subsections 20.2.1 through 20.2.3 outline the function of each block of the key source controller/
decoder.
Figure 20-2. Example of Key Matrix Configuration
Key source output pin
Key source input pin
20.2.1 Key source data register (KSR)
The key source data register sets the key source output data of the pin that outputs a key source signal.
Data is set to the key source data register via the data buffer.
When data is set to this register, the key source data is output from the LCD15/KS15/PYA15 to LCD0/KS0/PYA0
pins.
For details, refer to 20.3.
20.2.2 Segment signal/key source signal output timing control block
The segment signal/key source signal output timing block controls the output timing of the key source and
segment signals of the LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins.
Whether a key source signal is used or not is specified by the LCD mode select register.
The key source signal is not output when LCD display is not used. In this case, the above pins output a low
level.
Whether LCD display is not used or not is specified by the LCD mode select register.
For details, refer to 20.4.
20.2.3 Key input control block and P0D port register
The key input control block detects the key input signals input to the P0D3/K3 to P0D0/K0 pins in synchronization
with key source signal output timing.
To output the key source signals from the LCD15/KS15 through LCD0/KS0 pins, therefore, the P0D3/K3 to P0D0/
K0 pins are used as key input pins.
The key input data is read by the P0D port register (address 73H of BANK0) in the data memory.
For details, refer to 20.5.
232
Data Sheet U10101EJ4V0DS