PD17012_15 Datasheet, PDF (218/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
19.2.3 Segment signal/key source signal output timing control block
The segment signal/key source signal output timing control block controls the segment signal output timing
of the LCD19/P2H0 through LCD0/KS0/PYA0 pins.
These pins output a low level when the LCD is not displayed.
Whether the LCD is displayed or not is selected by the LCD mode select register.
The segment signal/key source signal output timing control block controls the timing of the segment and key
source signals output from the LCD15/KS15 through LCD0/KS0 pins.
Whether the key source signals are used or not is selected by the LCD mode select register.
For details, refer to 19.5.
19.2.4 Segment signal/general-purpose output port select block
The segment signal/general-purpose output port select block selects whether each segment signal output
pin is used for LCD display (to output a segment signal) or as a general-purpose output port pin.
This selection is made by using the P2HSEL to P2ESEL flags of LCD port select register and PYASEL flag
of LCD mode select register.
For details, refer to 19.4 and 19.5.
19.2.5 Key source data register/port YA group register
The key source data register/port YA group register sets the key source output data that is output from the
LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins.
The key source signal output data is set by the key source data register (KSR: peripheral address 42H) via
the data buffer.
For details, refer to 20. KEY SOURCE CONTROLLER/DECODER.
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Data Sheet U10101EJ4V0DS