PD17012_15 Datasheet, PDF (255/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
21.3.4 Inputting signal to CE pin
The CE pin does not accept a low or high level of less than 110 to 165 µs to prevent malfunctioning due to
noise.
The level of the signal input to the CE pin can be detected by using the CE flag of the CE pin level judge register
(RF address 07H).
Figure 21-2 shows the relationship between the input signal and CE flag.
Figure 21-2. Relationship Between Signal Input to CE Pin and CE Flag
CE pin
H
L
CE flag
1
0
Less than 110 to 165 µs 110 to 165 µs Less than
110 to 165 µ s
110 to 165 µ s
CE reset
PLL operation enabled
PLL disabled
STOP s instruction disabled (NOP) STOP s instruction enabled
PLL disabled
STOP s instruction enabled (NOP)
CE reset is executed in synchronization
with next setting of timer carry FF
21.3.5 Configuration and function of CE pin level judge register
The CE pin level judge register detects the level of the signal input to the CE pin.
The configuration and function of this register are illustrated below.
Name
Flag symbol Address
b3 b2 b1 b0
CE pin level judge register 0 0 0 C 07H
E
Read/
write
R
0 Low level
1 High level
Detects level input to CE pin
Fixed to 0
Power-on
000–
Clock stop
–
CE reset
–
– : Determined depending on pin status
The CE flag is not affected by a low or high level of less than 110 to 165 µs.
Data Sheet U10101EJ4V0DS
253