PD17012_15 Datasheet, PDF (50/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
5.7.2 Function of general register pointer
The general register pointer specifies a general register in the data memory.
Figure 5-8 shows the address of the general register specified by the general register pointer.
As shown in the figure, the higher 4 bits of the general register pointer (RPH: address 7DH) specify a bank,
and the lower 3 bits (RPL: address 7EH) specify a row address.
Because the valid number of bits of the general register pointer is 5, the row addresses (0H to 7H) of BANK0
and BANK1 can be specified as general registers.
For details on the operations of the general registers, refer to 6. GENERAL REGISTER (GR).
Figure 5-8. Address of General Register Specified by General Register Pointer
General register pointer
(RP)
RPH
RPL
b3 b2 b1 b0 b3 b2 b1 b0
0 0M
S
B
LB
SC
BD
0000000
00001
00010
01011
01100
01101
10110
10111
Specifies row address of each bank
Specifies bank
Bank
Row address
0H
BANK0
1H
2H
3H
BANK1
4H
5H
6H
BANK2
7H
5.7.3 Notes on using general register pointer
The least significant bit of address 7EH (RPL) to which the general register pointer is allocated is used as
the BCD flag of the program status word.
When rewriting the value of RPL, therefore, pay attention to the value of the BCD flag.
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Data Sheet U10101EJ4V0DS