PD17012_15 Datasheet, PDF (224/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
19.5 Common Signal Output Timing Control Block and Segment Signal/Key Source Signal Output
Timing Control Block
Figure 19-8 shows the configuration of the common signal output timing control block and segment signal/key
source signal output timing control block.
The common signal output timing control block controls the output timing of the COM2 to COM0 signals.
The segment signal/key source signal output timing control block controls the output timing of the segment signals
and key source signals of the LCD19/P2H0 through LCD0/KS0/PYA0 pins.
The common and segment signals are output when the LCDEN flag of the LCD mode select register is 1. By clearing
the LCDEN flag to 0, therefore, all LCD displays can be turned off.
The key source signal is output when the KSEN flag of the LCD mode select register is 1.
When LCD display is not performed, the COM2 to COM0 and LCD19/P2H0 to LCD0/KS0/PYA0 pins output a low level.
Figure 19-9 shows the configuration and function of the LCD mode select register.
Figure 19-8. Configuration of the Common Signal Output Timing Control Block and
Segment Signal/Key Source Signal Output Timing Control Block
Port data
To segment signal/
general-purpose output
port select block
Segment signal
Segment signal
timing control
Port data
To segment signal/
general-purpose output
port select block
Segment signal/
key source signal
Segment signal _{timing control}
b0
LCDD19
b1
|
LCDD16
b2
Key source data register/
port YA group register
b0
LCDD15
b1
|
LCDD0
b2
LCDEN flag
Basic clock for
timing control
To common
signal
output pin
KSEN flag
Common signal
timing control
222
Data Sheet U10101EJ4V0DS