PD17012_15 Datasheet, PDF (135/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
To prevent this, a delay is actually provided to the rising of the BTM0CY flag setting pulse and falling of the basic
timer 1 interrupt pulse as shown in Figure 12-13 (b).
In the above example, therefore, skipping of the basic timer 1 interrupt is prevented, even if a CE reset is effected,
by performing the watch processing within 10 ms.
Because the BTM0CY flag setting pulse and basic timer 1 interrupt time setting pulse can be independently set
to 4 Hz (250 ms), 10 Hz (100 ms), 200 Hz (5 ms), or 1 kHz (1 ms), a time difference is provided as shown in Figure
12-14 and Table 12-1.
Consequently, if the basic timer 1 interrupt must be enabled even when a CE reset is effected, the servicing of
the basic timer 1 interrupt must be completed within the delay time of the pulse shown in Figure 12-14.
Figure 12-13. Timing Chart
(a)
H
CE pin
L
BTM0CY flag H
setting pulse L
Basic timer 1 ^H
interrupt pulse L
Basic timer 1 interrupt
(b)
Because the BTM0CY flag setting pulse rises, a CE
reset is effected here. As a result, the basic timer 1
interrupt is skipped once.
H
CE pin _L
BTM0CY flag H
setting pulse L
Basic timer 1 ^H
interrupt pulse L
Basic timer 1 interrupt
Basic timer 1 interrupt
Delay time: 10 ms in this case
CE reset
Because there is a delay of 10 ms between the
falling of the basic timer 1 interrupt pulse and the
rising of the BTM0CY flag setting pulse, if basic
timer 1 interrupt servicing is completed within 10
ms, the timer processing is executed normally,
even if a CE reset is effected.
Data Sheet U10101EJ4V0DS
133