PD17012_15 Datasheet, PDF (181/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16. PLL FREQUENCY SYNTHESIZER
The PLL (Phase Locked Loop) frequency synthesizer is used to lock the frequency in the MF (Medium
Frequency), HF (High Frequency), and VHF (Very High Frequency) bands to a specific frequency by comparing
phase differences.
16.1 Configuration of PLL Frequency Synthesizer
Figure 16-1 shows the block diagram of the PLL frequency synthesizer.
As shown in the figure, the PLL frequency synthesizer consists of an input select block, programmable divider
(PD), phase comparator (φ-DET), reference frequency generator (RFG), and charge pump.
By connecting these blocks with an external lowpass filter (LPF) and voltage-controlled oscillator (VCO), a
PLL frequency synthesizer is organized.
Figure 16-1. Block Diagram of PLL Frequency Synthesizer
Control register
Data buffer
Unlock detection
block
Input select
block
Programmable
divider
(PD)
Phase
comparator
(φ -DET)
Charge
pump
VCOH
VCOL
Reference
frequency generator
(RFG)
EO
Note
Voltage-controlled
oscillator
(VCO)
Lowpass filter
(LPF)
Note
Note External circuit
Data Sheet U10101EJ4V0DS
179