PD17012_15 Datasheet, PDF (193/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.6 PLL Disabled Status
The PLL frequency synthesizer stops operation (is disabled) while the CE pin (pin 7) is low.
When the PLL is disabled by the PLL reference clock select register, the PLL frequency synthesizer also stops
operation.
Table 16-2 shows the operation of each block under each PLL disable condition.
When the VCOL and VCOH pins are disabled by the PLL mode select register, only the VCOL and VCOH
pins are internally pulled down, and the other blocks operate.
Because the PLL reference clock select register and PLL mode select register are not initialized (but hold
the previous status) on CE reset, they are restored to the original status when the CE pin has once gone low
and then back high again after the PLL has been disabled.
To disable the PLL on CE reset, therefore, initialize these registers in the program.
The PLL is disabled at power-on reset.
Table 16-2. Operation of Blocks Under PLL Disable Conditions
Condition
Blocks
VCOL and
VCOH pins
Programmable
counter
Reference frequency
generator
Phase comparator
Charge pump
CE Pin = Low Level
(PLL Disabled)
Internally pulled down
Stops division
Stops output
Stops output
Floats error out pins
CE Pin = High Level
PLL Reference Clock Select Register = 1111B PLL Mode Select Register = 0000B
(PLL Disabled)
(VCOH, VCOL Disabled)
Internally pulled down
Internally pulled down
Stops division
Operates
Stops output
Operates
Stops output
Floats error out pins
Operates
Operates
However, usually outputs low
level because there is no input.
16.7 Using PLL Frequency Synthesizer
To control the PLL frequency synthesizer, the following data is necessary.
(1) Division mode:
Direct division (MF), pulse swallow (HF, VHF)
(2) Pin used:
VCOL, VCOH
(3) Reference frequency: fr
(4) Division ratio:
N
The following subsections 16.7.1 to 16.7.3 explain how to set the PLL data in each division mode (MF, HF,
and VHF).
Data Sheet U10101EJ4V0DS
191