PD17012_15 Datasheet, PDF (263/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
21.4.6 If two or more release conditions are simultaneously set
If two or more release conditions are simultaneously set, and if even one of the conditions is satisfied, the
halt status is released.
The method to identify the release condition that is satisfied when two or more release conditions are specified
is shown below.
Example
HLTINT
HLTTMR
HLTKEY
INTPIN
DAT 1000B
DAT 0010B
DAT 0001B
DAT 0004H
START:
BR
MAIN
ORG
INTPIN
; INT pin interrupt vector address symbol
; definition
Processing A
; INT pin interrupt processing
TMRUP
EI
RETI
; Basic timer 0 processing
Processing B
RET
KEYDEC:
; Key input processing
Processing C
MAIN:
RET
MOVT
PUT
SET2
SET2
SET1
LOOP:
EI
HALT
SKF1
CALL
SKF1
CALL
BR
DBF, @AR
KSR, DBF
KSEN, LCDEN
BTM0CK1, BTM0CK0
IP
; Sets key source output data (table reference)
; to key source data register (KSR)
; Embedded macro
; Multiplexes LCD segment signal output with
; key source signal output
; Embedded macro
; Sets basic timer 0 carry FF setting time to 1 ms
; Embedded macro
; Enables INT pin interrupt
HLTINT OR HLTTMR OR HLTKEY
; Specifies interrupt, basic timer 0, and key input
; as halt release conditions
BTM0CY
; Embedded macro
; Detects BTM0CY flag
TMRUP
; Basic timer 0 processing if set to 1
KEYJ
; Embedded macro
; Detects key input latch^Note
KEYDEC
; Key input processing if latched
LOOP
Note If the target key source output data is not output, the KEYJ flag is not set (1).
Data Sheet U10101EJ4V0DS
261