PD17012_15 Datasheet, PDF (235/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
20.3 Key Source Data Setting Block
20.3.1 Configuration of key source data setting block
Figure 20-3 shows the configuration of the key source data setting block.
Figure 20-3. Configuration of Key Source Data Setting Block
Address
Symbol
Data
Data buffer (DBF)
0CH 0DH 0EH
DBF3 DBF2 DBF1
M
S
B
0FH
DBF0
L
S
B
16
Peripheral address 42H
Key source data register
(KSR)
Key source data latch
20.3.2 Function of key source data setting block
The key source data setting block sets the key source data to be output from the LCD15/KS15/PYA15 to LCD0/
KS0/PYA0 pins.
The key source data is set to the key source data register (KSR: peripheral address 42H) via the data buffer.
Each bit of the key source data register corresponds to the LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins, and
sets the key source data of each pin.
When a bit of the key source data register is set to 1, the pin corresponding to this bit outputs a high level
as a key source signal; when the bit is reset to 0, the corresponding pin outputs a low level.
For the output timing, refer to 20.4.
The following subsections 20.3.3 explains the configuration and function of the key source data register.
Also refer to Figure 19-5 in 19. LCD CONTROLLER/DRIVER.
Data Sheet U10101EJ4V0DS
233