PD17012_15 Datasheet, PDF (310/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
AC Programming Characteristics (TA = 25°C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.5 V)
Parameter
Symbol Note 1
Conditions
MIN.
TYP.
MAX.
Unit
Address setup time^{Note 2} (to MD0↓)
tAS
tAS
MD1 setup time (to MD0↓)
tM1S
tOES
Data setup time (to MD0↓)
tDS
tDS
Address hold time^{Note 2} (from MD0↑) tAH
tAH
Data hold time (from MD0↑)
tDH
tDH
Delay time from MD0↑ to data output float tDF
tDF
2
µs
2
µs
2
µs
2
µs
2
µs
0
130
ns
VPP setup time (to MD3↑)
VDD setup time (to MD3↑)
tVPS
tVDS
tVPS
tVCS
2
µs
2
µs
Initial program pulse width
tPW
tPW
0.95
1.0
1.05
ms
Additional program pulse width
MD0 setup time (to MD1↑)
tOPW
tM0S
tOPW
tCES
0.95
21.0
ms
2
µs
Delay time from MD0↓ to data output
MD1 hold time (from MD0↑)
MD1 recovery time (from MD0↓)
Program counter reset time
CLK input high-/low-level widths
tDV
tM1H
tM1R
tPCR
tXH, tXL
tDV
tOEH
tOR
—
—
MD0 = MD1 = VIL
tM1H + tM1R ≥ 50 µs
2
2
10
0.125
1
µs
µs
µs
µs
µs
CLK input frequency
Initial mode setting time
MD3 setup time (to MD1↑)
MD3 hold time (from MD1↓)
MD3 setup time (to MD0↓)
fX
tI
tM3S
tM3H
tM3SR
—
—
2
—
2
—
2
— Program memory read
2
4.19
MHz
µs
µs
µs
µs
Delay time from address^{Note 2} to data output tDAD
tACC
Program memory read
Hold time from address^{Note 2} to data output tHAD
tOH
Program memory read
0
MD3 hold time (from MD0↑)
tM3HR
— Program memory read
2
Delay time from MD3↓ to data output float tDFR
— Program memory read
2
Reset setup time
tRES
10
2
µs
130
µs
µs
µs
µs
Notes 1. Symbol of corresponding µPD27C256A (the µPD27C256 is a maintenance product).
2. The internal address signal is incremented by 1 on the 3rd fall of a four-clock input (CLK) cycle, and is not
connected to a pin.
308
Data Sheet U10101EJ4V0DS