PD17012_15 Datasheet, PDF (273/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
22.3 CE Reset
CE reset is effected when the CE pin goes high.
When the CE pin goes high, the RESET signal is output in synchronization with the rising edge of the next
basic timer 0 carry FF setting pulse, and the device is reset.
When CE reset is effected, the RESET signal initializes the program counter, stack, system register, and
some control registers, and the program is executed starting from address 0000H.
For the value to which each of the above registers is initialized, refer to the description of each register.
The operation of CE reset differs depending on whether the clock stop instruction is used.
The differences in operation are explained in the following subsections 22.3.1 and 22.3.2.
Subsection 22.3.3 explains the points to be noted on using CE reset.
22.3.1 CE reset when clock stop (STOP s) instruction is not used
Figure 22-2 shows the operation of CE reset when the clock stop (STOP s) instruction is not used.
When the STOP s instruction is not used, the basic timer clock select register of the control registers is not
initialized.
After the CE pin has gone high, therefore, the RESET signal is output at the rising edge of the basic timer
0 carry FF setting pulse (1 ms, 5 ms, 100 ms, 250 ms) selected at that time, and the device is reset.
Figure 22-2. CE Reset Operation When Clock Stop Instruction Is Not Used
5V
VDD
0V
H
CE
L
H
XOUT
L
Basic timer 0 carry
H
FF setting pulse
L
H
IRES
L
H
RES
L
H
RESET
L
Normal operation
Normal
operation
CE reset is effected at rising of basic
timer 0 carry FF setting pulse.
If selected basic timer 0 carry FF setting time is tSET,
this period “t” is 0 < t < tSET depending on timing of rising of CE pin.
During this period, program operation continues.
Data Sheet U10101EJ4V0DS
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