PD17012_15 Datasheet, PDF (182/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.2 Functional Outline of PLL Frequency Synthesizer
The PLL frequency synthesizer divides a signal input from the VCOH or VCOL pin by using the programmable
divider and outputs a phase difference from the reference frequency from the EO pin.
The PLL frequency synthesizer operates only when the CE pin is high, and is disabled when the CE pin is
low.
For details of the disabled status of the PLL frequency synthesizer, refer to 16.6.
The following subsections 16.2.1 through 16.2.6 outline the function of each block of the PLL frequency
synthesizer.
16.2.1 Input select block
This block selects the pin from which a signal output from an external voltage-controlled oscillator is input.
As the input pin, the VCOH or VCOL pin is selected by the PLL mode select register (RF address 21H).
For details, refer to 16.3.
16.2.2 Programmable divider
The programmable divider divides the signal input from the VCOH or VCOL pin at the division ratio set by
the program.
Two types of division modes can be selected: direct division and pulse swallow modes.
The division mode is selected by the PLL mode select register.
The division ratio is set by the PLL data register (PLLR: peripheral address 41H) via the data buffer.
For details, refer to 16.3.
16.2.3 Reference frequency generator
This generator generates a reference frequency to be compared by the phase comparator.
Twelve types of reference frequencies can be selected by using the PLL reference clock select register (RF
address 31H).
For details, refer to 16.4.
16.2.4 Phase comparator and unlock detection block
The phase comparator compares the division signal output by the programmable divider with the signal from
the reference frequency generator, and outputs a phase difference.
The unlock detection block detects the unlock status of the PLL.
The unlock status of the PLL is detected by the PLL unlock FF judge register (RF address 05H).
For details, refer to 16.5.
16.2.5 Charge pump
The charge pump outputs the signal output by the phase comparator to the EO pin as a high-level, low-level,
or floating signal.
For details, refer to 16.5.
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Data Sheet U10101EJ4V0DS