PD17012_15 Datasheet, PDF (261/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
Example
HLTINT DAT
INTTM DAT
INTPIN DAT
1000B
0003H
0004H
; Symbol definition of halt condition
; Interrupt vector address symbol definition
; Interrupt vector address symbol definition
START:
ORG
ORG
; Program address 0000H
BR
MAIN
INTTM
; 12-bit timer interrupt vector address (0003H)
BR
INTTIMER
INTPIN
; INT pin interrupt vector address (0004H)
Processing A
; Interrupt processing by INT pin
BR
INTTIMER:
EI_RETI
Processing B
; Interrupt processing by 12-bit timer
EI_RETI:
EI
RETI
MAIN:
SET2
SET2
LOOP:
IPTM, IP0
; Embedded macro
BTM1CK1, BTM1CK0
; Embedded macro
; Sets time interval of 12-bit timer to 1 ms
Processing C
; Main routine processing
EI
HALT
; <1>
BR
; Enables all interrupts
HLTINT ; Specifies releasing halt by interrupt
LOOP
In this example, the halt status is released when the 12-bit timer interrupt is acknowledged, and processing
B is executed. When the INT pin interrupt is acknowledged, processing A is executed.
Each time the halt status is released, processing C is executed.
If the INT pin interrupt request and 12-bit timer interrupt request are issued at the same time in the halt status,
processing A of the INT pin, which has the higher hardware priority, is executed.
If “RETI” is executed after execution of processing A, execution restores to the BR LOOP instruction in <1>,
but the BR LOOP instruction is not executed, and the 12-bit timer interrupt is immediately acknowledged.
If “RETI” is executed after processing B of the 12-bit timer interrupt has been executed, the BR LOOP
instruction is executed.
Data Sheet U10101EJ4V0DS
259