PD17012_15 Datasheet, PDF (39/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
Table 4-1. Data Memory Manipulation Instructions
Function
Operation
Addition
Subtraction
Logical
Compare
Transfer
Judgement
Instruction
ADD
ADDC
SUB
SUBC
AND
OR
XOR
SKE
SKGE
SKLT
SKNE
MOV
LD
ST
SKT
SKF
4.3 Addressing of Data Memory
Figure 4-3 shows addressing of the data memory.
An address of the data memory is specified by a bank, a row address, and a column address.
The row and column addresses are directly specified by using a data memory manipulation instruction. The
bank is specified by the contents of the bank register.
For details of the bank register, refer to 5. SYSTEM REGISTER (SYSREG).
Figure 4-3. Addressing of Data Memory
Data memory address
Bank
Row Address Column Address
b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0
Bank
M
register
Instruction operand
Data Sheet U10101EJ4V0DS
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