PD17012_15 Datasheet, PDF (108/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
11.6.2 Timing chart for acknowledging interrupt
Figure 11-9 shows the timing chart illustrating acknowledging interrupts.
(1) in this figure illustrates how one interrupt is acknowledged.
(a) in (1) shows the case where the interrupt request flag is the last to be set to 1, and (b) in (1) shows the
case where the interrupt enable flag is the last to be set to 1.
In either case, the interrupt is acknowledged when each of the interrupt request flag, interrupt enable flip-
flop, and interrupt enable flag are set to 1.
If the last flag or flip-flop that was set to 1 satisfies the first instruction cycle of the MOVT DBF, @AR instruction
or a given skip condition, the interrupt is acknowledged after the second instruction cycle of the MOVT DBF,
@AR instruction or the instruction that is skipped (NOP) has been executed.
The interrupt enable flip-flop is set in the instruction cycle next to the one in which the EI instruction is
executed.
(2) in Figure 11-9 illustrates how more than one interrupt is used.
In this case, the interrupts are sequentially acknowledged according to the hardware priority if all the interrupt
enable flags are set. The hardware priority can be changed by manipulating the interrupt enable flag by
program.
“Interrupt cycle” shown in Figure 11-9 is a special cycle in which the interrupt request flag is reset, a vector
address is specified, and the contents of the program counter are saved after an interrupt has been acknowledged,
and lasts for 4.44 µs, which is equivalent to the execution time of one instruction.
For details, refer to 11.7 Operations After Acknowledging Interrupt.
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Data Sheet U10101EJ4V0DS