PD17012_15 Datasheet, PDF (278/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
22.4.1 Power-on reset during normal operation
Figure 22-5 (a) shows the operation.
As shown in the figure, the power-on-clear signal is output and the device operation stops regardless of the
input level of the CE pin, if the supply voltage VDD drops below 3.5 V.
If VDD rises beyond 3.5 V again, the program starts from address 0000H after 50 ms of halt status.
“Normal operation” is when the clock stop instruction is not used and includes the halt status that is set by
the halt instruction.
22.4.2 Power-on reset in clock stop status
Figure 22-5 (b) shows the operation.
As shown in the figure, the power-on-clear signal is output and the device operation stops if supply voltage
VDD drops below 2.3 V.
However, it seems as if the device operation has not changed because the device is in the clock stop status.
When supply voltage VDD rises beyond 3.5 V next time, the program starts from address 0000H after a 50
ms halt.
22.4.3 Power-on reset when supply voltage VDD rises from 0 V
Figure 22-5 (c) shows the operation.
As shown in the figure, the power-on-clear signal is output until supply voltage VDD rises from 0 V to 3.5 V.
When VDD rises beyond the power-on-clear voltage, the crystal oscillator starts operating, and the program
starts from address 0000H after a 50 ms halt.
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Data Sheet U10101EJ4V0DS