PD17012_15 Datasheet, PDF (217/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
19.2 Functional Outline of LCD Controller/Driver
The LCD controller/driver can display up to 60 dots by using a combination of common signal output pins
(COM2 to COM0) and segment signal output pins (LCD19/P2H0 to LCD0/KS0/PYA0).
Figure 19-2 shows the relationship between common signal output pins, segment signal output pins, and
display dots.
As shown in this figure, three dots can be displayed at the intersections between one segment line and the
COM2 to COM0 pins.
The driving mode is 1/3 duty, 1/2 bias, and the drive voltage is supply voltage VDD.
The segment signal output pins (LCD19/P2H0 to LCD0/KS0/PYA0) can also be used as general-purpose output
port pins.
When these pins are used as general-purpose output port pins, ports 2H (LCD19/P2H0), 2G (LCD18/2G0), 2F
(LCD17/P2F0), 2E (LCD16/P2E0), and YA (LCD15/KS15/PYA15 to LCD0/KS0/PYA0) can be independently used.
Of the segment signal output pins, the LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins are also used as key source
signal output pins.
The key source signals and LCD segment signals are output by means of time-division multiplexing.
For details of the general-purpose output ports, refer to 10. GENERAL-PURPOSE PORTS.
For details of the key source signals, refer to 20. KEY SOURCE CONTROLLER/DECODER.
The following subsections 19.2.1 through 19.2.5 outline the function of each block of the LCD controller/
driver.
Figure 19-2. Common Signal Output, Segment Signal Output, and Display Dots
COM2 pin
COM1 pin
COM0 pin
Display dot
Segment signal output pin (LCDn)
19.2.1 LCD segment register
The LCD segment register sets dot data that is used to turn on/off the LCD.
Because this register is mapped in the data memory, it can be controlled by any data memory manipulation
instruction.
When the segment signal output pins are used as general-purpose output port pins, this register sets output
data.
For details, refer to 19.3.
19.2.2 Common signal output timing control block
The common signal output timing control block controls the common signal output timing of the COM2, COM1,
and COM0 pins.
These pins output a low level when the LCD is not displayed.
Whether the LCD is displayed or not is selected by the LCD mode select register (RF address 10H).
For details, refer to 19.4.
Data Sheet U10101EJ4V0DS
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