PD17012_15 Datasheet, PDF (277/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
22.4 Power-on Reset
Power-on reset is effected when the supply voltage VDD of the device rises from a specific level (called power-
on-clear voltage).
If the supply voltage VDD is lower than the power-on-clear voltage, a power-on clear signal (POC) is output
from the voltage detector shown in Figure 22-1.
When the power-on-clear voltage is output, the crystal oscillator is stopped, and the device operation is
stopped.
While the power-on-clear signal is output, the IRES, RES, and RESET signals are output.
If supply voltage VDD exceeds the power-on-clear voltage, the power-on-clear signal is cleared, and crystal
oscillation is started. At the same time, the IRES, RES, and RESET signals are also cleared.
At this time, the halt status is set to be released by the basic timer 0 carry due to the IRES signal. Therefore,
power-on reset is effected at the rising edge of the next basic timer 0 carry FF setting signal.
The basic timer 0 carry FF setting signal is initialized to 100 ms by the RESET signal. For this reason, reset
is effected 50 ms after supply voltage VDD has exceeded the power-on-clear voltage, and the program is started
from address 0.
This operation is illustrated in Figure 22-4.
The program counter, stack, system register, and control registers are initialized as soon as the power-on-
clear signal has been output.
For the value to which each of the above registers is to be initialized, refer to the description of each register.
The power-on-clear voltage is 3.5 V (rated value) during normal operation, and 2.3 V (rated value) in the clock
stop status.
The operations performed when the power-on-clear voltage is at the respective levels are explained in 22.4.1
and 22.4.2.
The operation to be performed if the supply voltage VDD rises from 0 V is explained in 22.4.3.
Figure 22-4. Operation of Power-on Reset
5V
VDD
0V
Power-on clear voltage
H
CE
L
H
XOUT
L
Basic timer 0 carry
H
FF setting pulse
L
H
Power-on clear signal
L
H
IRES
L
H
RES
L
H
RESET
L
Normal operation
Device operation stops Halt status
50 ms
Power-on clear released
Oscillation starts
Power-on reset
Program starts
from address 0.
Data Sheet U10101EJ4V0DS
275