PD17012_15 Datasheet, PDF (197/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.8 Status on Reset
16.8.1 On power-on reset
The PLL is disabled on power-on reset because the PLL reference clock select register is initialized to 1111B.
16.8.2 On execution of clock stop instruction
The PLL is disabled when the CE pin goes low.
16.8.3 On CE reset
(1) CE reset after execution of clock stop instruction
The PLL is disabled because the PLL reference clock select register is initialized to 1111B by the clock stop
instruction.
(2) CE reset without clock stop instruction executed
Because the PLL reference clock select register retains the previous status, the previous status is restored
as soon as the CE pin has gone high.
16.8.4 In halt status
The set status is retained if the CE pin is high.
Data Sheet U10101EJ4V0DS
195