PD17012_15 Datasheet, PDF (262/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
Caution
When executing the HALT instruction that will set the release condition where by the halt status
is released by the setting of the interrupt request flag (IRQ×××) when the interrupt enable flag
(IP×××) is set, describe a NOP instruction immediately before the HALT instruction.
If a NOP instruction is described immediately before the HALT instruction, a time of one
instruction is generated in between the IRQ××× manipulation instruction and HALT instruction.
In the case of the CLR1 IRQ××× instruction, for example, clearing IRQ××× is correctly reflected
on the HALT instruction (refer to Example 1 below). If a NOP instruction is not described
immediately before the HALT instruction, the CLR1 IRQ××× instruction is not correctly reflected
on the HALT instruction, and the HALT mode is not set (refer to Example 2 below).
Example 1. Program that correctly executes HALT instruction
CLR1
NOP
IRQ×××
HALT
1000B
; Sets IRQ×××
; Describes NOP instruction immediately before
; HALT instruction
; (clearing IRQ××× is correctly reflected on HALT
; instruction)
; Correctly executes HALT instruction
; (HALT mode is set)
2. Program that does not set HALT mode
CLR1
HALT
IRQ×××
1000B
; Sets IQR×××
; Clearing IRQ××× is not reflected on HALT instruction
; (but on instruction next to HALT)
; HALT instruction is ignored (HALT mode is not set)
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Data Sheet U10101EJ4V0DS