PD17012_15 Datasheet, PDF (284/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
22.6 Power Failure Detection
Power failure detection is used to judge whether power-on reset by application of supply voltage VDD, or CE
reset has been effected when the device is reset, as shown in Figure 22-9.
Because the contents of the data memory and ports are undefined on power application, these contents are
initialized by means of power failure detection.
A power failure can be detected in two ways: by using the power failure detector to detect the BTM0CY flag,
and by detecting the contents of the data memory (RAM judgement).
22.6.1 and 22.6.2 explain how a power failure is detected by using the power failure detector and BTM0CY
flag.
22.6.3 and 22.6.4 explain how a power failure is detected by RAM judgement method.
Figure 22-9. Power Failure Detection Flow Chart
Program starts
Power
failure detection
Not power
failure
Power failure
Initializes data
memory and
output ports
22.6.1 Power failure detector
The power failure detector consists of a voltage detector, a basic timer 0 carry disable flip-flop that is set by
the output (power-on-clear signal) of the voltage detector, and a basic timer 0 carry, as shown in Figure 22-1.
The basic timer 0 carry disable FF is set to 1 by the power-on-clear signal, and is reset to 0 when an instruction
that reads the BTM0CY flag is executed.
When the basic timer 0 carry disable FF is set to 1, the BTM0CY flag is not set to 1.
When the power-on-clear signal is output (at power-on reset), the program is started with the BTM0CY flag
reset, and the BTM0CY flag is disabled from being set until an instruction that reads the BTM0CY flag is
executed.
Once the instruction that reads the BTM0CY flag has been executed, the BTM0CY flag is set each time the
basic timer 0 carry FF setting pulses has risen. It can be judged whether power-on reset (power failure) or CE
reset (not power failure) has been effected by detecting the contents of the BTM0CY flag when the device is
reset. Power-on reset has been effected if the BTM0CY flag is reset to 0; CE reset has been effected if it is
set to 1.
The voltage at which a power failure can be detected is the same as the voltage at which power-on reset is
effected, or VDD = 3.5 V during crystal oscillation, or VDD = 2.3 V in the clock stop status.
Figure 22-10 shows the transition of the status of the BTM0CY flag.
Figures 22-11 and 22-10 show the timing chart and the operation of the BTM0CY flag.
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Data Sheet U10101EJ4V0DS