PD17012_15 Datasheet, PDF (190/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.5 Phase Comparator (φ-DET), Charge Pump, and Unlock Detection Block
16.5.1 Configuration of phase comparator, charge pump, and unlock detection block
Figure 16-4 shows the configuration of the phase comparator, charge pump, and unlock detection block.
The phase comparator compares the divided frequency output “fN” of the programmable divider with the
reference frequency output “fr” of the reference frequency generator, and outputs an up request (UP) or down
request (DW) signal.
The charge pump outputs the output of the phase comparator from the error out (EO) pin.
The unlock detection block detects the unlock status of the PLL frequency synthesizer.
The following subsections 16.5.2 to 16.5.4 explain the operations of the phase comparator, charge pump,
and unlock detection block respectively.
Figure 16-4. Configurations of Phase Comparator, Charge Pump, and Unlock Detection Block
PLLUL flag
Reference frequency
fr
generator
fN
Programmable divider
UP
Phase comparator
(^φ -DET)
DW
Unlock FF
Charge pump
EO
PLL disable signal
16.5.2 Function of phase comparator
As shown in Figure 16-4, the phase comparator compares the divided frequency output “fN” of the
programmable divider with the reference frequency output “fr” of the reference frequency generator, and outputs
an up request or down request signal.
If the divided frequency fN is lower than the reference frequency fr, the phase comparator outputs the up
request signal; if fN is higher than fr, it outputs the down request signal.
Figure 16-5 shows the relationship among the reference frequency fr, divided frequency fN, up request signal,
and down request signal.
When the PLL is disabled, neither the up request nor down request signal is output.
The up request and down request signals are respectively input to the charge pump and unlock detection
block.
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Data Sheet U10101EJ4V0DS