PD17012_15 Datasheet, PDF (280/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
22.5 Relationship Between CE Reset and Power-on Reset
There is a possibility that power-on reset and CE reset are effected at the same time when power is first
applied.
The reset operations performed at this time are explained in 22.5.1 through 22.5.3.
22.5.4 explains the points to be noted in raising supply voltage VDD.
22.5.1 If VDD pin and CE pin rise simultaneously
Figure 22-6 (a) shows the operation.
At this time, the program starts from address 0000H due to power-on reset.
22.5.2 If CE pin rises in forced halt status of power-on reset
Figure 22-6 (b) shows the operation.
At this time, the program starts from address 0000H due to power-on reset in the same manner as in 22.5.1.
22.5.3 If CE pin rises after power-on reset
Figure 22-6 (c) shows the operation.
At this time, the program starts from address 0000H due to power-on reset, and the program starts from
address 0000H again at the rising of the next basic timer 0 carry FF setting signal because of CE reset.
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Data Sheet U10101EJ4V0DS