PD17012_15 Datasheet, PDF (192/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.5.4 Unlock detection block
As shown in Figure 16-4, the unlock detection block detects the unlock status of the PLL frequency
synthesizer by using the up request or down request signal from the phase comparator.
Because either of the up request or down request signal outputs a low level in the unlock status, this low-
level signal is used to detect the unlock status.
In the unlock status, the unlock flip-flop (FF) is set to 1.
The unlock status is detected by the PLL unlock FF judgement register (refer to 16.5.5).
The unlock FF is set at the cycle of reference frequency fr selected at that time.
When the contents of the PLL unlock FF judge register are read (by the PEEK instruction), the unlock FF is
reset (Read & Reset).
Therefore, the unlock FF must be detected at a cycle longer than the cycle 1/fr of the reference frequency
fr.
16.5.5 Configuration and function of unlock FF judge register
Name
PLL unlock FF judge
register
Flag symbol
b3 b2 b1 b0
000P
L
L
U
L
Address
Read/
write
05H R & Reset
Detects status of unlock FF
0 Unlock FF = 0: PLL lock status
1 Unlock FF = 1: PLL unlock status
Fixed to 0
Power-on
Clock stop
CE
0 0 0 Undefined
Retained
Retained
This register is a read-only register and is reset when its contents are read to the window register by the PEEK
instruction.
Because the unlock FF is set at the cycle of reference frequency fr, the contents of the PLL unlock FF judge
register must be written to the window register at a cycle longer than the cycle 1/fr of the reference frequency
fr.
The delay of the phase comparator up/down request signal is fixed to between 0.8 µs and 1.0 µs.
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Data Sheet U10101EJ4V0DS