PD17012_15 Datasheet, PDF (186/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
16.3.4 Programmable divider and PLL data register
The programmable divider divides the signal input from the VCOH or VCOL pin by the value set to the swallow
counter and programmable counter.
The swallow counter and programmable counter are 4-bit binary down counters.
The division ratio is set to the swallow counter and programmable counter by the PLL data register (PLLR:
peripheral address 41H) via data buffer.
Data is set to or read from the PLL data register by using the PUT PLLR, DBF or GET DBF, PLLR instruction.
The value to be divided is called N value.
For how to set the N value in each division mode, refer to 16.7.
(1) PLL data register and data buffer
The relationship between the PLL data register and data buffer is explained next.
In the direct division mode, the higher 12 bits are valid, and all 16 bits are valid in the pulse swallow mode.
In the direct division mode, all the higher 12 bits are set to the programmable counter.
In the pulse swallow mode, the higher 12 bits are set to the programmable counter, and the lower 4 bits are
set to the swallow counter.
(2) Relationship between division value N and divided output frequency
The relationship between the value “N” set to the PLL data register and the frequency “fN” of the signal divided
and output by the programmable divider is as follows.
For details, refer to 16.7.
(a) In direct division mode (MF)
fIN
fN =
N
N: 12 bits
(b) In pulse swallow mode (HF and VHF)
fIN
fN =
N
N: 16 bits
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Data Sheet U10101EJ4V0DS