PD17012_15 Datasheet, PDF (210/320 Pages) Renesas Technology Corp – 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DIGITAL TUNING SYSTEM HARDWARE

µPD17012, 17P012
17.5 Error of External Gate Counter
The external gate counter has an internal frequency error and count error, as described in (1) and (2) below.
(1) Internal frequency error
The internal frequency of the external gate counter is created by dividing the 4.5 MHz system clock frequency.
Therefore, if this frequency has an error of “+x” ppm, the internal frequency accordingly has an error of “+x”
ppm.
(2) Count error
The external gate counter counts the frequency at the rising edge of the internal frequency.
Therefore, if the internal frequency is at low level when the gate is opened (when the input signal of the pin
rises), one extra pulse is counted.
However, this extra pulse may not be counted, depending on the count level of the internal frequency, when
the gate is closed (when the input signal of the pin rises next time).
Therefore, the count error is “+1, −0”.
17.6 Status on Reset
17.6.1 On power-on reset
The P1B3/FMIFC and P1B2/AMIFC pins are set in the general-purpose input port mode.
The P0B3/FCG1 and P0B2/FCG0 pins are set in the general-purpose I/O port mode.
17.6.2 On execution of clock stop instruction
The P1B3/FMIFC and P1B2/AMIFC pins are set in the general-purpose input port mode.
The P0B3/FCG1 and P0B2/FCG0 pins are set in the general-purpose I/O port mode.
17.6.3 On CE reset
The P1B3/FMIFC, P1B2/AMIFC, P0B3/FCG1, and P0B2/FCG0 pins retain the previous status.
17.6.4 In halt status
The P1B3/FMIFC, P1B2/AMIFC, P0B3/FCG1, and P0B2/FCG0 pins retain the status immediately before the
halt status was set.
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Data Sheet U10101EJ4V0DS