Z80180 Datasheet, PDF (99/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
84
Return from Subroutine (RETI) Instruction Sequence
When the EDH/4DH sequence is fetched by the Z8X180, it is recognized as
the RETI instruction sequence. The Z8X180 then refetches the RETI
instruction with four T-states in the EDH cycle allowing the Z80
peripherals time to decode that cycle (See Figure 42). This procedure
allows the internal interrupt structure of the peripheral to properly decode
the instruction and behave accordingly.
The M1E bit of the Operation Mode Control Register (OMCR) must be
set to 0 so that M1 signal is active only during the refetch of the RETI
instruction sequence. This condition is the desired operation when Z80
peripherals are connected to the Z8018X.
T1 T2 T3 T1 T2 T3 Ti Ti Ti T1 T2 T3 Ti T1 T2 T3 T1
Phi
A0–A18 (A19)
D0–D7
PC
EDH
PC + 1
4DH
PC
EDH
PC + 1
4DH
M1 (M1E = 1)
M1 (M1E = 0)
MREQ
RD
ST
Note: RETI machine cycles 9 and 10 not shown.
Figure 42. RETI Instruction Sequence
The RETI instruction takes 22 T-states and 10 machine cycles. Table 10
lists the conditions of all the control signals during this sequence for the
UM005001-ZMP0400