Z80180 Datasheet, PDF (91/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
76
Phi
INT0
A0–A19
Last MC
INT0 acknowledge cycle
RST instruction execution
PC is pushed onto stack
T1 T2 TW* TW* T3 Ti Ti T1 T2 T3 _T1 T2 T3
PC
SP-1
SP-2
M1
MREQ
RD
WR
IORQ
D0–D7
MC: Machine Cycle
RST instruction
PCH
PCL
*Two Wait States are automatically inserted
Note: The TRAP interrupt occurs if an invalid instruction is fetched
during Mode 0 interrupt acknowledge. (Reference Figure 36.)
Figure 36. INT0 Mode 0 Timing Diagram
INT0 Mode 1
When INT0 is received, the PC is stacked and instruction execution
restarts at logical address 0038H. Both IEF1 and IEF2 flags are reset to 0,
UM005001-ZMP0400