Z80180 Datasheet, PDF (315/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
299
Table 57. Internal I/O Registers (Continued)
Register
Mnemonics Address
Remarks
DMA Memory Address
Register
Channel 1B:
MAR1B
2 A Bits 0 - 2 are used for MAR1B
DMA I/O Address Register IAR1L
Channel 1L:
2B
DMA I/O Address Register IAR1H
Channel 1H
2C
DMA Byte Count Register BCR1L
Channel 1L:
2E
DMA Byte Count Register
Channel 1H:
BCR1H
2F
DMA Status Register:
DSTAT
DMA Mode Register:
DMODE
30
bit
DE1
DE0 DWE1 DWE0 DIE1 DIE0 —
DME
during RESET 0
0
1
1
R0/W
0
1
0
R/W
R/W R/W
W
W
R/W
R
DMA Master enable
DMA Interrupt Enable 1,0
31
DMA Enable Bit Write Enable 1,0
DMA enable ch 1,0
bit
—
—
DM1 DM0 SM1 SM0 MMOD —
during RESET 1
R/W
1
0
0
0
0
0
1
R/W
R/W R/W
R/W R/W
Memory MODE select
Ch 0 Source Mode 1,0
Ch 0 Destination Mode 1,0
DM1,0
00
01
10
11
MMOD
0
1
Destination
M
M
M
I/O
Address
DAR0+1
DAR0-1
DAR0 fixed
DAR0 fixed
Mode
Cycle Steal Mode
Burst Mode
SM1,0
00
01
10
11
Source
M
M
M
I/O
Address
SAR0+1
SAR0-1
SAR0 fixed
SAR0 fixed
UM005001-ZMP0400