Z80180 Datasheet, PDF (216/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z8018x Family
MPU User Manual
200
PH I
CPU or DMA Re ad/W rite Cycle (O nly DMA W rite Cycle for TENDi)
T₁
T₂
T_W
T₃
T₁
D REQ1
(le ve lsens e )
D REQ1
(e dge s e ns e )
45
45 46^**
47
TENDi
ST
DMA Cycle 17
Starts
46^*
CPU Cycle
Starts
18
48
Note s :
*T_DRQS and T_DRQH are spe cified for th e rising e dge ofth e clock follow e d by T₃.
**T_DRQS and T_DRQH are s pe cified for th e rising edge ofth e clock .
Figure 84. DMA Control Signals
UM005001-ZMP0400