Z80180 Datasheet, PDF (152/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
137
Bit
Position Bit/Field R/W Value Description
2
Break
R/W 0 Break Feature Enable On
Feature
1 Break Feature Enable Off
Enable
1
Break
R/W 0 Break Detect On
Detect
1 Break Detect Off
(RO)
0
Send
R/W 0 Normal Xmit
Break
1 Drive TXA Low
Each ASCI channel control register B configures multiprocessor mode,
parity and baud rate selection.
ASCI0 Time Constant Low Register (I/O Address: 1AH) (Z8S180/L180-Class Processors
Only)
Bit
7
6
5
4
3
2
1
0
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
ASCI0 Time Constant High Register (I/O Address: 1BH) (Z8S180/L180-Class Processors
Only)
Bit
7
6
5
4
3
2
1
0
R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Reset
0
0
0
0
0
0
0
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
UM005001-ZMP0400