Z80180 Datasheet, PDF (86/326 Pages) Zilog, Inc. – Z8018x Family MPU

Z 8018x Fam ily
M PU Us e r M anual
71
Phi
A0–A19
D0–D7
MI
MREQ
RD
WR
stacked PC-1. If UFO is 1, the starting address of the invalid instruction is
equal to the stacked PC-2.
Bus Release cycle, Refresh cycle, DMA cycle, and WAIT cycle cannot be
inserted just after TTP state which is inserted for TRAP interrupt
sequence. Figure depicts TRAP Timing - 2nd Op Code undefined and
Figure illustrates Trap Timing - 3rd Op Code undefined.
2nd Op Code
Fetch Cycle
PC Stacking
Restart from 0000H
Op Code
Fetch Cycle
T1 T2 T3
Ti Ti Ti Ti Ti T1 T2 T3 T1 T2 T3 T1 T2 T3
PC
Undefined
Op Code
SP-1
PCH
SP-2
PCL
0000H
Figure 32. TRAP Timing Diagram -2nd Op Code Undefined
UM005001-ZMP0400